Pulse circuits



Dec. 11, 1962 B. G. GLAzER ETAL PULSE CIRCUITS .fl Z4 4 I4 /z M1593 Malzin lz a v14 Il l! id Il ll 'Il IllIII I l vl TTTTTTTTTT l I Il lll'/Mvw' P//ui I" l rdiff/nza c/ecz//rr ra amm/me .lil u INVUVTOR- EDWARD LNasser:

Dec. 1l, 1962 Filed June 19, 1959 B. G. GLAZER ETAL PULSE CIRCUITS 3Sheets-Sheet 2 EDWHRD T. Nssen 6 BURTDN E. ELHZER Dec. 11, 1962 B. G.GLAzr-:R ETAL 3,068,405

PULSE CIRCUITS s sheets-sheet s Filed June 19, 1959 United States PatentOfifiee 3,068,405 Patented Dec. 11, 1962 3,068,405 PULSE CIRCUITS BurtonG. Giazer, Collingswood, and Edward J. Nossen, Haddonfield, NJ.,assignors to Radio Corporation of America, a corporation of DelawareFiled `lune 19, 1959, Ser. No. 322,98; 8 Claims. (Cl. 324-68) and otherpulse-type, distance determining systems.

A typical embodiment of the present invention includes a delay linehaving a sending end and a mismatched receiving end. The intervalbetween two pulses is measured `by applying the pulses to the sendingend and determining the point along the line lat which the firstapp-lied pulse (which passes down the line and is reflected from thereceiving end of the line) is time coincident with the second appliedpulse. One preferred pulse position determining circuit includes aplurality of taps on the delay line and a diode connected to each tapand biased to conduct only upon the coincidence of two pulses.

in a form of the invention employed `for pulse width determination, theinput pulse is first differentiated to produce one pulse coincident withthe leading edge of the input pulse and another pulse coincident withthe lagging edge of the input pulse. These pulses are of oppositepolarity. The delay line employed is short-circuited its receiving endso that the first applied pulse is reiiected from the receiving end inreverse polarity. Accordingly, the reiiected leading edge pulse is ofthe correct polarity to add to the second applied lagging edge pulse andthe point at which the two `are coincident can readily be sensed.

The invention will be described in greater detail by reference to thefollowing description taken in connection with the accompanying drawingin which:

FiG. l is a block and schematic circuit diagram or one form of thepresent invention;

FIG. 2 is a block circuit diagram of another form or the presentinvention;

FIG. 3 is la drawing of waveforms present at various points in thecircuit of FIG. 1;

FIG. 4 is a more complete block diagram of an embodiment of theinvention suitable for determining pulse width; and

FIG. 5 is a schematic circuit diagram of the circ-uit shown in blockform in FiG. 4.

Similar reference numerals are applied to similar elements throughoutthe figures.

FIGS. 1 and 3 `should be referred to first. input pulses 1d, 12 lareapplied to the input terminal 14 of amplifier 16. The first pulse 10,the one occurring at r=0, is positive going `and the second pulse i2 isnegative going. These may be derived from `a square pulse the width ofwhich is to be determined or from separate sources as, for example,separate transmitting stations. it is desired to determine the intervalof time between pulses 1@ and i2.

Amplifier 16 amplifies and inverts pulses 16 and 12 and applies them tothe sending end of delay line 18. The delay line is terminated in itscharacteristic impedance I?.c `at its sending end and is short-circuitedat its receiving end. Accordingly, each of the input pulses is reflectedwhen it reaches the receiving end and is also reversed in polarity inthe process.

A plurality of equally spaced terminals 2t) are connected to the delayline and diodes 22 are connected to said terminals. The anodes of thediodes lare connected to terminals 20 and the cathodes are connectedthrough resistors 24 to a source of biasing voltage r-|-E. The value ofthe biasing voltage is such that the coincidence of two positive pulses`at a diode is required to cause that diode to conduct.

The circuit operation may more readily be understood by referring toFIG. 3. The ordinate in FIG. 3 is representative of pulse amplitude andthe abcissa of the pulse position along the delay line. At time 1:0 thefirst pulse 1.0 which is of negative polarity is at the sending end ofthe delay line. After a time t=r, where 'r is the one Way delayintroduced by the line, pulse 10 is at the receiving end of the-line. Ashort time x later, pulse 10 is reflected from the short-circuitedreceiving end of the line and appears in reverse polarity as shown inFIG. 3c. Shortly thereafter (t=T-ly) the second pulse 12 is applied tothe sending end of the delay line. As can oe seen in FIG. 3d, pulse .l2is traveling toward the receiving end of the line and pulse 10 istraveling toward the sending end. At time t=frf,z, pulses 10 and 12appear at the same point on the delay line, as shown in FlG. 3e. The twopulses together are of sufficient amplitude to overcome the bias on oneof the diodes, whereby that diode conducts and an output volt-ageappears at the output terminal 26 of that diode. This pulse is a digitalindication of the spacing lbetween the two input pulses and it may beapplied, after proper processing, to a computer or other indicatingdevice. The positions of the pulses a short time later is shown in FIG.3g.

Referding again to FIG. 1, relay line 10 is terminated yat its sendingend in an impedance R which, taken with the `amplifier impedance,terminates the line in its characteristic impedance. The reflectedpulses are therefore not re-reflected from the sending end and do notcause undesirable extraneous transients. However, as will be explainedin more detail later, it is desirable for some purposes to select thereference (first) pulse of a pair of pulses and to recirculate it.Circuits are shown later which accomplish such recirculation.

The embodiment shown in FIG. 2 is capable of measuring the time intervalbetween two pulses 30, 32 of the same polarity. These pulses 4areapplied from terminal 14 through amplifier 16 to delay line 34. Thisdelay line is terminated at its sending end in its characteristicimpedance Rc and at its receiving end in an open circuit. Thus, thepulses reflected from the receiving end are of the same polarity asthose reaching the receiving end.

Threshold circuits 36 are similar to those illustrated in FIG. l. Thepolarity of the diodes are dependent upon the polarity of the inputpulses. In the embodiment chosen -for illustration, the pulses appliedto the delay line are of negative polarity and accordingly, the diodesshould have their cathodes connected to the delay line terminals andtheir -anodes to the biasing voltage. The biasing voltage, in this case,is negative rather than positive.

A circuit for pulse width determination is shown in PEG. 4. Squarepulses or at least pulses with steep leading t' and lagging edges areapplied to input terminal 40. These are differentiated by differentiator42 and the differentiated pulses (two for each square Wave) are appliedthrough a driver-ampliiier 44 to a short-circuited delay line 46. Thefirst differentiated pulse of each pair is of one polarity and thesecond of opposite polarity. One of the diodes in threshold circuit 48will be rendered conductive, the particular one depending upon the inputsquare pulse width. The resultant digital signal is applied to computerSi).

In some cases the duration of the input square pulse and accordingly thespacing between the pair of differentiated pulses derived from thesquare pulse may be longer than twice the delay line duration. ln thesecases, it is desira to recirculate the first pulse until there iscoincidence between the first pulse and the later occurring pulse. Thisrecirculation is accomplished by a feedback connection d2 from a diodeclose to the sending end of the delay line. The diode is properly poledto sense the first pulse after it is reflected from the receiving end ofthe delay line. The reflected pulse is applied through a pulse shaperand amplifier 54 to the input end of delay line 46. The shaper andamplifier introduce a delay sufficient to make the regenerated pulseoccur precisely 2T later than the reference pulse, where 21- is the timerequired for a pulse to travel from the receiving to the sending end ofthe delay line. EEG. 3g shows the regenerated pulse position at time27--l-x.

It will be remembered that the first or reference pulse of each pair ofpulses applied to the delay line of one polarity and the second pulse ofthe pair is of another polarity. Accordingly, in the arrangement inwhich the reference pulse is continuously circulated, some means must beprovided for discriminating against the second pulse. This is the reasonfor blocking pulse generator S6 connected between the driver-amplifierand the pulse Shaper and amplifier 54. The blocking pulse generatorsenses the second pulse and, in response thereto, renders the pulseShaper and amplifier 54 inoperative for a period sufficient to permitthe second pulse to pass the terminal to which lead 52 is connected.

A schematic diagram of the circuit shown in block form in FIG. 4 isillustrated in FIG. 5.

A negative going square pulse 60 is applied to input terminal 40. Thepulse passes through coupling capacitor 62 to a differentiator 42. Theelements of the difierentiator include a resistor l64, inductance 66 andcapacitor 68. The output of the differentiator consists of a negativegoing pulse 70 coincident with the leading edge of the square pulse anda positive going pulse 72 coincident with the lagging edge of the squarepulse. For the purposes of the discussion which follows, pulse 7() ishereinafter referred to as the leading edge pulse and pulse 72 isreferred to as the lagging edge pulse.

The leading and lagging edge pulses are applied to the base i4 oftransistor '76. This transistor has two outputs the first at its emitter78 and the second at its collector Sli. The pulses at emitter 78 are ofthe same polarity as the input pulses and they are applied through abalanced transistorized driver amplifier 8i to the sending end 82 ofdelay line 46. In the amplification process, the leading and laggingedge pulses 70 and 72 respectively are reversed in polarity as shown inthe sketch.

The leading edge pulse 7) travels down delay line 46 and is reiiectedfrom the far or receiving end in negative polarity. For the present inmay be assumed that the interval between pulses 7G and 72 is less than lmicrosecond, the round trip delay time of the delay line 46. In thiscase, at some point along the line, the leading edge pulse, afterreflection from the receiving end S4 of the line, will be in timecoincidence with the lagging edge pulse 72. The coincident pulses willbe of negative polarity and will appear at one of the taps. Assume for amoment that the pulses appear at the second tap 86. These pulses areapplied from tap 86 via lead 88 to the diode 9i?. As has been previouslyexplained, diode 90 and all corresponding diodes are biased to a pointsuch that the coincidence of two pulses are required to make the diodeconduct. Thus, when the coincident pulses appear at lead @8 and areapplied to the cathode of the diode, they pass through the diode and areapplied to the base 92 of transistor 94.

The negative pulse applied to base 92 of the transistor 94 is ofsuf'licient amplitude to drive the transistor' into heavy conduction.During the conducting interval, the capacitor 96 in the emitter circuitchar Upon the termination of the coincident pulses app to the base 5?2of transistor 94, capacitor 96 disch through rcsistor 98, therebymaintaining the emitter u tt of transistor 94 negative with respect toits previous value, and the transistor 94 is abruptly driven to cutoff.The cessation of collector current is sensed as a change of collectorvolt- This change in voltage appears as a pulse at lead i512. its widthcan be adjusted by choice of circuit coinponents and it may be matchedto the speed capability of external circuits.

Although diodes are shown connected only to the first two taps of thedelay line, it will be appreciated that each tap is connected to a diodelike 9% and each diode is connected to a transistor like 94. For thepurpose of drawing simplicity, these are illustrated by the single block164 in the dashed block legended threshold circuits 48. loreover, thethreshold circuits are connected to a computer 56 which is shown in FIG.4 but is not shown in HG. 5.

Returning now to the left of FlG. 5, it will be remembered thattransistor '76 has two outputs. The first, that is, the output at theemitter 78 has been discussed above. The second output which appears atcollector S0 is inverted in polarity. The leading edge pulse is nowpositive and it cannot pass through diode 108. The lagging edge pulse72, however, is negative and it passes through diode 108 to thetransistorized blocking pulse generator 56. The latter amplifies andstretches input pulse 72 to an extent suflicient to prevent the laggingedge pulse 72 from passing through pulse Shaper and amplifier 54 as willbe explained in greater detail shortly. rThis stretched pulse is appliedvia lead 110 to the emitter 112 of the output transistor 114 in stage54.

Pulse amplifier and shaper 54 is the means for recirculating pulses inthe delay line. Por the purpose of the present discussion, assume nowthat the leading and lagging edge pulses are spaced an interval greaterthan l microsecond from one another. In this case, if the leading edgepulse were not recirculated when it reached the sending end of the lineafter reflection from the receiving end, the leading and lagging edgepulses would never be coincident. According to a feature of the presentinvention, the leading edge pulse 70, after reflection from thereceiving end 84, arrives back at input terminal 86. This pulse is nowof negative polarity and passes from terminal 86 via lead 116 throughdiode 118 to the transistorized blocking oscillator stage following. Theoutput transformer of the blocking oscillator includes a tertiarywinding 122 which is connected in a manner to invert the output pulsewith respect to the input trigger signal. This inverted, shaped pulse124, which appears at the collector 126 of the transistor 114 is appliedvia lead 128 to the sending end 82 of the delay line. The delayintroduced is sufficient so that the regenerated pulse is applied to thesending end exactly l microsecond after the leading edge pulse 70.

The lagging edge pulse 72 is of negative polarity when travelling fromthe sending end 82 of the delay line toward the receiving end 84. Thus,when it arrives at terminal 86, it is of proper polarity to be able topass through diode 118 of the pulse Shaper and amplifier 54.Accordingly, if

n.; but.

the pulse Shaper and amplifier 54 remained operative, the

lagging edge pulse 72 would be recirculated which would be undesirable.However, as was explained previously, the lagging edge pulse 72 passesthrough blocking pulse generator 56 and the stretched and shaped pulsewhich results is applied to the emitter 112. This pulse is of the properpolarity to cut off transistor 114 and prevent recirculation of aregenerated lagging edge pulse 72.

summarizing briefly the operation of the circuit described in detailabove, the input square pulse 60 is differentiated in stage 42 andsubsequently amplified to the proper power level in stage 80. Theleading edge pulse 70 passes down the delay line and is reflected fromthe short-circuited receiving end 84. If the delay interval is lmicrosecond or less, there is coincidence at one of the etaps of thedelay line. The coincident pulses pass through a diode 90 to atransistor 94. The shaped output pulse results which may be applied to acomputer. If the delay interval between pulses 70 and 72 is greater thanl microsecond, the leading edge pulse is recirculated in the delay lineby pulse Shaper and amplifier 54. The number of times the pulse isrecirculated may be counted by a counter connected to lead 130. Thelagging edge pulse is prevented from being recirculated by blockingpulse amplifier 56.

It will be noted that an RLC differentiator 64, 66, 68 is used insteadof an RC differentiator. This RLC differentiator is critically dampedand it is preferred because it has a definite resonant frequency. Thispermits the leading and lagging edge pulse widths to be accuratelycontrolled. The actual width desired depends upon the spacing of thedelay line taps.

The computer S (FIG. 4) connected to the collectors of the thresholdcircuit stages (FIG. may be of known type. For example, it may includean input bank of bistable multivibrators all of which are normally resetand one of which is subsequently set in response to an output pulse fromone of these stages. Even more simply, an indicator consisting of a bankof neon lamps or the like may be employed to show the tap at whichcoincidence occurs.

The recirculation counter may also be of known type. The total delaybetween leading and lagging edge pulses is, of course, n(2v)l-A1, wheren is the number of times the leading edge pulse recirculates; 2T is theround-trip delay time of the delay line; and Ar is time required aftern(2r) for the leading and lagging edge pulses to become coincident atone of the taps. It is measured simply by noting the particular tap atwich coincidence occurs. The counter may be turned off in response to asignal appearing at one of leads ltlZ and the delay line may be clearedof pulses in the same manner. For example, stage 114 may be blocked forl mierosecond or so in response to such a pulse by a circuit likeblocking pulse generator 56.

The speed of the basic circuit is considered in deciding whether abinary counter, a decimal counter or other device is used for thecounter connected to lead 102. A typical decimal counter uses a beamswitching tube for speeds up to l microsecond. Binary counters may be ofthe bistable dip-flop variety.

In a practical circuit, the pulses sent down the line had a width at the50% amplitude. point of about twice the time delay between taps. Sincethe pulses were almost triangular dueto the frequency limiting responseto the delay line and amplifiers, the width of the combined coincidentpulse at the threshold level was only somewhat more than the delay timebetween taps. The combined width is preferably greater than the delaytime in order always to obtain an output on at least one tap.

In the embodiment chosen for illustration, l0 taps are shown. It shouldbe appreciated that this is meant to be illustrative rather thanlimiting since more or fewer than this number may be used. Ten taps areconvenient if decimal readout is desired.

It has been found possible using the circuits described above to obtainvery precise pulse measurements. In an embodiment of the inventionemploying a 0.5 microsecond delay line (1.0 microsccond round trip) ithas been found possible to measure pulse spacing to an accuracy of i005microsecond. The widths of the pulses were slightly greater than 0.05microsecond. Pulse measurement to this precision has importantapplications in digital shoran and other very precise distancedetermining systems. In these applications the precise measurementarrangement described is employed as an interpolation method for de- 6termining a fraction of an interval between two clock pulses.

The circuits described may also be used in digital earlylate gatemeasuring systems. ln these applications, an on target measurement canbe made to produce a signal at a center tap on the delay line andearly-late gate measurements to produce signals at terminals on eitherside of the center terminal.

The present invention has been found to be especially useful in themillimicrosecond region where other pulse measuring methods fail. Italso has been possible to measure intervals longer than 21, the roundtrip period, by counting the number of times the first reference pulseis regenerated by the amplifier as previously explained.

What is claimed is:

l. Apparatus for determining the interval between two pulses comprising,in combination, a delay line having a sending end and a mismatchedreceiving end; means for applying said pulses to said sending end;andmeans for determining the point along the line at which the firstapplied pulse is time coincident with the second applied pulse, saidlast means including a plurality of pulse coincidence responsive deviceseach connected to a different point along said delay line.

2. Apparatus for determining the interval between two pulses, one of onepolarity and the other of the other polarity comprising, in combination,a delay line having a sending end and terminated at its receiving end ina short-circuit; means for applying said pulses to said sending end; andmeans for determining the point along the line at which the firstapplied pulse is time coincident with the second applied pulse, saidlast means including a plurality of pulse coincidence responsive deviceseach connected to a different point along said delay line.

3. Apparatus for determining the interval between two pulses comprising,in combination, a delay line having a plurality of equally spacedterminals along its extent and which is mismatched at its receiving end;means for applying said pulses to the sending end of said delay line insuch polarity that the first pulse after reflection from the mis-matchedend of said line will be of the same polarity as the second pulse at thetime said second pulse is applied to said line; and a plurality ofbiased diodes, one connected to each terminal, and each poled to conductupon the coincidence of two pulses of the same polarity at the terminalto which it is connected.

l 4. A circuit for determining the width of a pulse, said circuitcomprising, in combination, means for differentiatinU said pulse toobtain a first pulse coincident with the leading edge thereof and thesecond pulse of opposite polarity coincident with the lagging edgethereof; a delay line having a sending end and a short-circuitedreceiving end; means for applying said pulses to said sending end,whereby when the rst pulse is reflected from the shortcircuited end ofthe delay line, it is of the same polarity as the second pulse; andmeans for determining the point along the line at which the firstapplied pulse is time coincident with the second applied pulse.

5. A circuit for determining the width of a pulse, said circuitcomprising, in combination, means for differentiating said pulse toobtain a first pulse coincident with the leading edge thereof and thesecond pulse of opposite polarity coincident with the lagging edgethereof; a delay line having a sending end and a short-circuitedreceiving end; means for applying said pulses to said sending end,whereby when the first pulse is reflected from the shortcircuited end ofthe delay line, it is of the same polarity as the second pulse; meansnear the sending end of said line for receiving pulses reflected fromthe short-circuit end thereof and applying them in reverse polarity tothe sending end of said line, whereby said reflected pulses arerecirculated in the line; and means for determining the point aionG theline at which said first pulse is time coincident with said secondpulse.

6. Apparatus for determining the interval between two pulses comprising,in combination, a delay line having a sending end terminated in itscharacteristic impedance and a mismatched receiving end; means forapplying said pulses to said sending end; and means for determining thepoint along the line at which the rst applied pulse is time coincidentwith the second applied pulse, said last means including a plurality ofpulse coincidence responsive devices each connected to a different pointalong said delay line.

7. Apparatus as set forth in claim 6, wherein said lreceiving end isterminated in a short-circuit.

8. Apparatus as set forth in claim 6, wherein said receiving end isterminated in an open circuit.

References @ted in the tile or lnis patent UNETED STATES PATeNTS TaddeoSept. 22, 1959

